Yet Another Apple2+ in an FPGA

I've recreated my old Apple ][+ in an FPGA. I know it's been done before but I got this Spartan 3AN Starter Board a few weeks ago and I needed a project to get used to the tools and to dust off my Verilog and FPGA skills.

Features:

• Built in a Spartan 3AN Starter Board evaluation kit.
• Implemented in Verilog, synthesised by Xilinx ISE 9.2i WebPACK tools.
• My own 6502 implementation.
• 640x400 @ 60 Mhz VGA output. An Apple2 has a 280x192 pixel display so I doubled each pixel and centered it in the screen.
• PS/2 keyboard input is converted to Apple key codes.
• 12K Apple ROMs placed in Spartan 3 internal block RAMs.
• 24K of on-chip RAM in block RAMs.
• Uses roughly 19% of logic of an xc3s700an-5 Spartan 3 FPGA (but almost all the onboard block RAMs.).

The 6502 is clocked at 50 Mhz. In an Apple ][ it runs at 1Mhz. My implementation has an extra execute cycle and a wait state for synchronous memory reads so it runs about 20 times as fast as a normal Apple 2. I've also added an optional 20 cycle wait state generator (enabled by one of the toggle switches) to slow down the processer so it will act more like a normal Apple (otherwise the "beep" becomes a "click").

The source code is here: apple2fpga.tgz A pre-generated .bit file is here: apple2.bit

I wouldn't have been able to do it if I hadn't saved this reference manual through countless moves.